Asic design engineer

Synopsys in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to join their digital interface IP group. Responsibilities include defining verification specifications, test bench design, test case creation, and contributing to technical reviews. Qualifications include an MS in EE with 3+ years of experience, expertise in System Verilog and UVM, and knowledge of USB protocol. The base salary ranges from $122,000 to $182,000 per year with additional benefits. Inclusion and diversity are valued.